在現代的多核心系統中，晶片內網路(Network-on-Chip; NoC)已經普遍成為晶片之間的標準通訊架構。隨著製程進步到深次微米(Deep Sub-Micron)與三維晶片(3-D IC)架構，良率與可靠度成為一個關鍵的設計考量，因此針對大型多核心系統設計一個可擴充、具成本優勢的晶片內網路容錯架構，遂成為一個重要的課題。冗餘的技巧已廣泛的被應用在解決上述良率與可靠度的問題。但隨著晶片內網路的規模變大，傳統的微架構層級冗餘(Microarchitecture Level Redundancy; MLR)會遭遇到成本與擴充性上面的問題。在本文中，我們提出一種新穎的容錯方式，使用路由器層級冗餘(Router Level Redundancy; RLR)，在大規模的晶片網路架構下，此設計具有硬體成本、結構化、與易於實作等優勢。本文先利用2-D SoC的架構，說明路由器層級冗餘的基本概念，之後再擴充到目前最先進的3-D IC架構，並利用在3-D IC下獨有的解構方式，創造出更大的頻寬資源，且利用此資源提出更細緻(fine-grained)的路由器冗餘架構。在效能分析上，我們使用最重要的評量標準來驗證我們所提的架構：包含良率(Yield)與可靠度(Reliability)。實驗結果顯示，我們的設計在這幾項評量上有顯著的進步，更重要的是，隨著晶片內網路的規模增大，我們所提架構的增益越大，同時平均的成本卻又同時下降，這項有價值且稀有的特性，更顯示我們的架構，適合大型的多核心晶片內網路設計。

In the modern manycore systems, networks-on-chip (NoC) has evolved as the de facto standard for chip level communication infrastructure. As yield and reliability worsen in deep sub-micron (DSM) and three-dimensional (3-D) IC era, it is critical to provide a scalable and cost effective fault-tolerant scheme for large-scale NoC based manycore systems. Redundancy techniques are widely adopted to address these yield/reliability issues. As the size of NoC increases, traditional microarchitecture level redundancy (MLR) suffers from the cost and scalability issues. In this paper, we propose an innovative router level redundancy (RLR) scheme which is cost effective, structural, and easy to implement for large-scale NoC. To the best of authors’ knowledge, it is the first time to introduce the concept of router level redundancy in the context of reliable NoC design. To demonstrate the applicability of RLR, we first adopt 2-D SoC to explain the fundamental ideas. Then, we extend the architecture to the 3-D IC regime. In 3-D IC, extra bandwidth can be created through dimensional decomposition process. We exploit this extra resource for a fine-grained RLR architecture. To convince our design, the mesh-based architecture is evaluated with most important fault tolerance benchmarks: yield, and reliability. Experimental results show that our design has remarkable improvement on those metrics, and most importantly, the gain of the proposed scheme increases with the growth of NoC size but the relative cost decreases at the same time. This rare and valuable characteristic convinces our scheme suitable for large-scale NoC design.