本論文提出並實現一寬頻功率可調式(Power Scalable)十位元管線化類比數位轉換器(Pipelined ADC)，其使用一新的可調頻寬運算放大器技術。透過調整運算放大器之偏壓電流，使其隨著類比數位轉換器之取樣頻率等比例地改變，在避免讓電晶體操作在弱反轉區下，來達成功率可調的功能。此晶片實現於1.2伏特65奈米CMOS製程。佈局後的模擬結果顯示，當取樣頻率從100MS/s降到25MS/s時，晶片整體功率消耗也隨之從21.4毫瓦降到9.8毫瓦，且在整個取樣頻率範圍內，SNDR皆可維持在 58dB 以上。此晶片在取樣頻率 100MSPS 和輸入頻率 20.7MHz 下， FoM 達到0.29pJ/conversion-step。

A high-bandwidth power-scalable 10-bit pipelined ADC utilizing a newly-proposed bandwidth-reconfigurable operational amplifier (OPAMP) is presented and verified. The converter accomplishes power-scaleable functionality by varying the bias currents of the opamps in proportion to the converter sampling frequency without pushing MOS transistors into a weak inversion regime. Post-layout simulation in a 1.2-V 65-nm CMOS process shows that power consumptions is scaled from 21.4 mW (100
MS/s) to 9.8 mW (25 MS/s) while maintaining an SNDR more than 58 dB over the entire sampling frequency range. The converter achieves 0.29 pJ/conversion-step for a sampling rate of 100-MS/s and an input
frequency of 20.7 MHz.