在管線化類比數位轉換器(Pipelined Analog-to-Digital Converter)中，使用不完全穩定並且沒有迴轉(Incomplete-Settling-Without-Slewing)技術，由我們的分析中與SPICE驗證可以得知，運算放大器(Operational Amplifiers；Opamps)，在整個放大週期中，使用多位元的級數，可以避免迴轉並且擁有線性穩定的特性。如果運算放大器沒有經過迴轉的過程，其頻寬不足所產生的誤差，可以視為一固定的增益誤差，因此可以被簡單的線性數位校準系統(Digital Calibration)所校正。此技術不只可以藉由節省頻寬與增益的需求，來達到節省功率消耗的效果，也可以藉由簡單線性的數位演算法，來減少數位校準系統中，所需要的收斂時間，在此論文中，作者以台積電的0.13um製程，設計了11位元 200MS/s的類比數位轉換器，第一級被設計成頻寬不足，而第二級則是符合頻寬需求，並且在後面緊接著9位元的理想ADC，由模擬結果發現，在前兩級的功率消耗只有29mW，使用線性數位校準演算法，其有效位元數(ENOB)可以由5.73位元改善到10.83位元，而其收斂時間為40,000次循環。

A pipelined analog-to-digital converter (ADC) using an incomplete-settling-without-slewing technique is proposed and verified by SPICE simulations. Our analysis shows that operational amplifiers (Opamps) in
multi-bits stages can avoid slewing and linearly settle for whole period of amplification. If opamp does not experience slewing, the error caused by incomplete settling can be regarded as a constant gain error, which can be compensated by linear digital calibration scheme. This technique not only can reduce the power consumption of the opamp by relieving its bandwidth and gain requirements, but also can decrease the
convergence time of digital calibration algorithms by employing a simple linear calibration scheme. The prototype 11-bit 200-MS/s ADC is designed in TSMC’s 0.13um 1P8M process. First stage is designed with
insufficient bandwidths and followed by a complete-settling stage and a 9-bit ideal ADC. The SPICE simulation results show the power consumption in the first two stages is 29mW and an effective-number-of-bits (ENOB) is improved from 5.73 bits to 10.83 bits by linear digital calibration within 40,000 iterations.